New ideas are all around us, but only a few will change the world. That’s our focus at JPL. We ask the biggest questions, then search the universe for answers—literally. We build upon ideas that have guided generations, then share our discoveries to inspire generations to come. Your mission—your opportunity—is to seek out the answers that bring us one step closer. If you’re driven to discover, create, and inspire something that lasts a lifetime and beyond, you’re ready for JPL.
Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.
This outstanding opportunity is part of the Autonomous Systems Division's Flight Electronics Group
which crafted the electronics for the latest Mars rover and helicopter (Perseverance & Ingenuity). Come join a team that proved flying on Mars is possible.
As an FPGA Engineer Lead V (industry equivalent title: Senior Principal FPGA Designer)
, you will lead the planning and execution of highly sophisticated and unique electronics systems with Laboratory wide impact.Specific Responsibilities Include
This Position Requires The Following Qualifications
- Improve FPGA design and verification flow
- Improve hardware resilience techniques
- Apply sophisticated digital design knowledge and principles to complex designs
- Advise on advanced memory program
- Advise on multi-processor architectures and memory coherence
- Mentor junior engineers
- Bachelor’s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 12 years of related experience; Master’s in similar disciplines with a minimum of 10 years of related experience; or PhD in similar disciplines with a minimum of 8 years of related experience
- Very strong experience architecting, designing, implementing, and testing advanced digital systems
- Extensive experience crafting FPGAs and embedded processors designs using tools: Synplify Pro/Premier, Xilinx Vivado, Microsemi Libero SoC, and Mentor Graphics Questa design suite
- Demonstrated experience developing teams, presenting in design reviews and quarterly management reviews
- Experience leading FPGA designs through full life cycle from initial concept to burn review.
- Success infusing new design/verification technologies and methodologies
- Experience in bus standards protocol such as: sRIO, SpaceWire, PCI, MILSTD-1553, CAN, and Ethernet
- Experience designing with radiation tolerant Xilinx and Microsemi FPGAs
- Skillfully handles fast pace and dynamic product development environment
- Outstanding leader able to build consensus as well as excellent written/verbal communication skills
- Embedded Software knowledge and experience
- SystemC or C++, Matlab
- Experience with digital twin modeling
- Familiar with Failure Analysis and worst-case analysis
JPL is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to sex, race, color, religion, national origin, citizenship, ancestry, age, marital status, physical or mental disability, medical condition, genetic information, pregnancy or perceived pregnancy, gender, gender identity, gender expression, sexual orientation, protected military or veteran status or any other characteristic or condition protected by Federal, state or local law.
In addition, JPL is a VEVRAA Federal Contractor.
EEO is the Law.
EEO is the Law Supplement
Pay Transparency Nondiscrimination Provision
The Jet Propulsion Laboratory is a federal facility. Due to rules imposed by NASA, JPL will not accept applications from citizens of designated countries or those born in a designated country unless they are Legal Permanent Residents of the U.S or have other protected status under 8 U.S.C. 1324b(a)(3). The Designated Countries List is available here.